This invention relates generally to floating gate memory devices such as an array of Flash electrically, erasable programmable read-only memory (EEPROM) cells. More particularly, it relates to a semiconductor integrated circuit memory device which includes wordline tracking structure for matching reference and sector core wordline voltages across the entire chip regardless of sector location.
As is generally known in the art, there exists a class of non-volatile memory devices referred to as "Flash EEPROMs" which has recently emerged as an important memory device by combining the advantages of EPROM density with EEPROM electrical erasability. Such Flash EEPROMs provide electrical erasing and a small cell size. In a conventional Flash EEPROM memory device, a plurality of one-transistor core cells may be formed on a semiconductor substrate in which each cell is comprised of a P-type conductivity substrate, an N-type conductivity source region formed integrally with the substrate, and an N-type conductivity drain region also formed integrally within the substrate. A floating gate is separated from the substrate by a thin dielectric layer. A second dielectric layer separates a control gate from the floating gate. A P-type channel region in the substrate separates the source and drain regions.
One type of architecture used for Flash memories is typically referred to as a NOR Flash memory architecture which is an array of Flash EEPROM cells (floating gate devices) which are divided into a plurality of sectors. Further, the memory cells within each sector are arranged in rows of wordlines and columns of bit lines intersecting the rows of wordlines. The source region of each cell transistor within each sector is tied to a common node. Therefore, all of the cells within a particular sector can be erased simultaneously and erasure may be performed on a sector-by-sector basis. The control gates of the cell transistors are coupled to wordlines, and the drains thereof are coupled to bit lines.
In order to program the Flash EEPROM cell in conventional operation, the drain region and the control gate are raised to predetermined potentials above the potential applied to the source region. For example, the drain region has applied thereto a voltage V.sub.D of approximately +5.5 volts with the control gate V.sub.G having a voltage of approximately +9 volts applied thereto. These voltages produce "hot electrons" which are accelerated across the thin dielectric layer and onto the floating gate. This hot electron injection results in an increase of the floating gate threshold by approximately two to four volts.
For erasing the Flash EEPROM cell in conventional operation, a positive potential (e.g., +5 volts) is applied to the source region. The control gate is applied with a negative potential (e.g., -8 volts), and the drain region is allowed to float. A strong electric field develops between the floating gate and the source region, and a negative charge is extracted from the floating gate to the source region by way of Fowler-Nordheim tunneling.
In order to determine whether the Flash EEPROM cell has been properly programmed or not, the magnitude of the read current is measured. Typically, in the read mode of operation the source region is held at a ground potential (0 volts) and the control gate is held at a potential of about +5 volts. The drain region is held at a potential between +1 to +2 volts. Under these conditions, an unprogrammed cell (storing a logic "1") will conduct a current level approximately 50 to 100 .mu.A. The programmed cell (storing a logic "0") will have considerably less current flowing.
For example, a 16 Mb (megabit) Flash memory core array is typically manufactured in the form of an N.times.M matrix on a single chip where N equals the number of rows and M equals the number of columns. Further, the memory core array may be divided into a left-half sector array and a right-half sector array. Each of the left-half and right-half sector arrays is formed of a number of sectors, such as sixteen, each defining a selectable block. Each sector is formed of a predetermined number of rows which are grouped together. For the 16 Mb array divided into sixteen sectors in the left-half sector array and sixteen sectors in the right-half sector array, each sector or block has a size of 512 rows and 1024 columns.
Such a typical 16 Mb memory core array 10 formed on a single chip 11 is illustrated in FIG. 1 which consists of a left-half sector array 12 and a right-half sector array 14. The left-half sector array 12 is composed of sixteen sectors, S0 through S15. Similarly, the right-half sector array 14 is composed of sixteen sectors, S16 through S31. Each of the sectors S0-S31 stores 512 K bits of data arranged in 512 rows and 1024 columns. As can be seen, the many sectors (S0-S31) are located individually across the entire chip 11. Thus, the distance between one corner sector (e.g., sector S24) and another corner sector (e.g., sector S23) is very long. As a result, the difference in locations between the various sectors in the memory core array 10 will create sensing problems during a Read mode of operation.
In particular, there is often required voltages to be internally generated that are greater than an external or off-chip power supply potential VCC which is supplied to it. For example, it is known that in Flash EEPROMs operating at VCC equal to +3.0 volts a high voltage of approximately +5.0 volts is needed to be produced for the reading mode of operation of the memory cells. As a consequence, the semiconductor memories also generally include an internal voltage boosting circuit for generating an output signal boosted to be higher than the external supply voltage. Such a voltage boosting circuit 16 is shown in FIG. 1 for generating a wordline supply voltage VPXG at node N1, which is passed to appropriate wordlines in the various sectors S0-S31 in the memory core array 10 via a row decoder 18.
The row decoder 18 is located centrally between the left-half sector array 12 and the right-half sector array 14. The row decoder is responsive to address signals for causing word drivers (not shown) to supply the wordline supply voltage VPXG from the boosting circuit 16 to the appropriate wordlines associated with the various sectors. The wordline supply voltage VPXG is typically in the range of +3.7 volts to +4.7 volts, which is raised above the input power supply potential VCC of typically +3.0 volts.
If it is assumed that the voltage boosting circuit 16 is positioned in a lower left-side portion of the chip 11, the sector S23 is located near to the boosting circuit 16 and the sector S24 is located very far from the boosting circuit. Thus, the wordline voltage VPXG1 on the wordline WL.sub.N at node N2 associated with the sector S23 will be substantially equal to the boosted voltage VPXG from the boosting circuit 16. This boosted voltage VPXG is a target voltage which is desired to be maintained across the entire chip. However, the wordline voltage VPXG2 on the wordline WL.sub.F at node N3 associated with the sector S24 will be substantially less than the target voltage for most of a sensing period during the Read mode of operation.
Further, it is assumed that a reference sector or mini-array 20 is generally positioned to be near to the boosting circuit 16. Thus, the reference wordline voltage on the wordline WL.sub.R at node N4 associated with the reference sector 20 will also be substantially equal to the boosted voltage VPXG. The reference sector or array 20 includes a plurality of reference cells arranged in rows and columns (e.g., 20.times.20). The resistor R1 represents a lumped resistive load associated with the conductor lead line 21 extending between the node N2 adjacent the "near" sector S23 and the node N3 adjacent the "far" sector S24. The capacitor C.sub.S represents the capacitive loading of a selected sector when it is connected to its associated wordline. The capacitor C.sub.S for the selected sector has the same value notwithstanding its location in the memory core array 10. The capacitor C.sub.R represents the capacitive loading at the input of the reference sector or array 20 and has a value which is much smaller than the capacitor C.sub.S.
For a high speed read operation, it is necessary to read the sector core cell during the settling time of the wordline voltages, before they have reached a D.C. steady state. Thus, optimal reading is successfully obtained when the voltages on the wordline WL.sub.R and WL.sub.F voltages closely follow each other. Therefore, when it is desired to compare the voltage VPXG on the reference wordline WL.sub.R at the reference or sector array 20 to the voltage VPXG2 on the wordline associated with the "far" sector S24, there will be obtained a large difference between them. This is due to the fact that there is a mismatch in the resistance and capacitance residing in the paths traveling from the boosting circuit 16 to the reference wordline WL.sub.R in the reference sector 20 and to the memory core wordline WL.sub.F in the "far" sector S24. As a consequence, there would be caused a poor sense margin in sensing circuitry (not shown) used during the Reading, particularly for sensing conducting memory core cells.
In view of this, there has arisen a need to provide a wordline tracking structure for matching the reference and sector core wordline voltages across the entire chip regardless of sector location. This is accomplished in the present invention by the provision of a second VPXG conductor line operatively connected between sector wordlines of a "far" sector and a reference cell mini-array. The second VPXG conductor line has a substantially smaller time constant than in a first VPXG conductor line operatively connected between an output of a booster circuit and the sector wordlines of the "far" sector.